1. Field of the Invention
The present invention relates to solid state circuits employing digital logic. More particularly, the present invention relates to programmable logic arrays employing CMOS field effect transistors.
2. Background of the Invention
Programmable logic arrays (PLAs) are a well-known method of implementing logic in complex digital circuits. Programmable logic arrays typically have a two "plane" structure, i.e. two separate regions or groupings of logic gates with the outputs from one region leading into the other. For example, a typical PLA comprises a plane of AND gates which leads into a plane of OR gates. Equivalently, the AND and OR planes may be implemented using NAND gates and inverters in one plane and NOR gates and inverters in the other plane. This type of two-plane PLA allows a large number of arbitrary logic equations to be implemented in an orderly manner. The orderly structure of PLAs is particularly advantageous in designing large scale integrated (LSI) or very large scale integrated (VLSI) systems.
The programming of a PLA may be achieved in several different ways. For example, in maskprogrammable PLAs the logic array may be built up on an integrated circuit chip using several masks in the formation of the chip. The final logic connections are left to one or two mask steps which can be relatively easily modified. Other more flexible systems, sometimes referred to as field programmable PLAs, use fuses which can be blown or electrically programmable transistors to allow programming after chip manufacture.
In designing complementary metal oxide semiconductor (CMOS) circuits, especially in VLSI applications, the space required for CMOS logic offsets some of the other advantages of CMOS circuitry. This is due to the general requirement in CMOS logic of using equal numbers of n and p channel transistors in designing ratioless CMOS logic gates. In general an N input logic gate implemented in CMOS will have 2 N transistors, N p type and N n type transistors. This results in considerable extra area required in the chip. Ratioed CMOS logic only requires N+1 transistors, typically N n type and one p type, but power is consumed even when the logic circuit is not switching. One technique which has been used to relax this requirement and reduce chip size utilizes a clock to control the operation of the logic gates. Such clocked logic is referred to as dynamic logic. Dynamic logic is described, for example, in William M. Penney, Lillian Lau, eds., MOS Integrated Circuits, Van Nostrand & Co. (1972), pp. 260-288.
In dynamic logic the logic gates are precharged to a predetermined voltage level during one phase of a clock signal and then during a separate "evaluation" clock phase the logic outputs of the gates are determined or evaluated from the logic inputs. The capacitive storage of charge in the transistors allows the retention of information between the precharge and evaluation clock phases. Since there is no continuous current flow in dynamic logic CMOS circuits, power dissipation is at a much lower level than would otherwise be the case in static ratioed CMOS design. Also, the general static CMOS requirement of equal numbers of n and p type transistors may be relaxed reducing the number of transistors per logic gate and reducing chip area.
A drawback of dynamic logic is that correctly synchronizing the precharge and evaluation functions of a dynamic CMOS circuit can raise difficult timing and design problems in complex circuits. Also, other design problems, such as charge sharing, may be present in complex dynamic CMOS circuits.